Circuit Emulation Service (“CES”) allows time division multiplexing (“TDM”) services such as DS-n and E-n circuits to be transparently extended across a packet network. With circuit emulation over IP, for example, TDM data received from an external device at the edge of an Internet Protocol (“IP”) network is converted to IP packets, sent through the IP network, passed out of the IP network to its destination, and reassembled into a TDM bit stream. One application of CES is the interconnection of enterprise private telephone networks at different sites. For example, CES over a packet network can be used to connect two private branch exchanges (“PBXs”) on two different campuses without having packet transport capabilities on the PBXs themselves. This inter-working allows voice traffic between the two campuses to use a packet network backbone instead of leased TDM lines, and also allows voice and data traffic to use the same packet network.
In order for CES to function properly it is desirable to achieve the same clock in both the transmitting and receiving ends of a TDM circuit from end-to-end such that, for example, the T1 stream of a downstream PBX transmits with the same clocking characteristics as the T1 stream of the upstream PBX. Known clocking techniques include both synchronous and asynchronous clocking modes, of which the asynchronous clocking modes include Differential Clock Recovery, Independent Clocking, Clock Recovery using Simple Timestamps, Adaptive Buffer-Fill-based Clock Recovery, and Adaptive Packet Inter-arrival Time Averaging-based Clock Recovery.
In the timestamp-based technique for clock synchronization, a master periodically sends explicit time indications or timestamps to a slave to enable the slave to synchronize its local clock to the transmitter's clock. This synchronization strategy allows multiple slaves, for example in a broadcast or point-to-multipoint communication scenario, to synchronize their clocks to the master. The master clock could consist essentially of an oscillator and a pulse counter. The oscillator issues periodic pulses that constitute the input to the pulse (timestamp) counter. The output of the counter represents the master clock signal and is incremented by a fixed amount at each pulse. Samples of master clock signals are communicated to the slave as timestamps. A receiving TDM terminal node employs an adaptive timing technique to reconstruct the timing signal of the transmitting TDM terminal from the timestamps. This is commonly done using a PLL that slaves the receiver clock to a transmitter clock. The PLL is able to process the transmitted timestamps to generate timing signal for the receiver. The purpose of the PLL is to estimate and compensate for the frequency drift occurring between the oscillators of the transmitter clock and the receiver clock. However, the presence of packet delay variation jitter and packet losses can affect the performance of the clock estimation/compensation process, making the transmitter clock appear faster or slower than it actually is, and ultimately, causing the propagation of some residual jitter up to the receiver clock signal.